IC Pin Modeling and Mitigation of ESD-Induced Soft Failures

Abstract

In this article, electrostatic discharge (ESD) induced soft failures (SFs) of a USB3 Gen1 device are investigated by direct transmission line pulse injection with varying pulsewidth, amplitude, and polarity to characterize the failure behavior of the interface and to create a SPICE model of the voltage and current waveform dependent failure thresholds. ESD protection by transient-voltage-suppression diodes is numerically simulated in several configurations. The results show viability of using well-established hard failure mitigation techniques for improving SF robustness. A good agreement between numerical simulation for optimized board design and measurements are achieved. A novel concept of SF system efficient ESD design is proposed and demonstrated to be effective for making decisions during early product development, in board designing and prototyping phase.

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Circuit Model; Electrostatic Discharge (ESD); SEED; Soft Failure (SF); SPICE; Transmission Line Pulse (TLP)

International Standard Serial Number (ISSN)

0018-9375; 1558-187X

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2021 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Apr 2021

Link to Full Text

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