Memristor-Based HTM Spatial Pooler with On-Device Learning for Pattern Recognition

Abstract

This article investigates hardware implementation of hierarchical temporal memory (HTM), a brain-inspired machine learning algorithm that mimics the key functions of the neocortex and is applicable to many machine learning tasks. Spatial pooler (SP) is one of the main parts of HTM, designed to learn the spatial information and obtain the sparse distributed representations (SDRs) of input patterns. The other part is temporal memory (TM) which aims to learn the temporal information of inputs. The memristor, which is an appropriate synapse emulator for neuromorphic systems, can be used as the synapse in SP and TM circuits. In this article, a memristor-based SP (MSP) circuit structure is designed to accelerate the execution of the SP algorithm. The presented MSP has properties of modeling both the synaptic permanence and the synaptic connection state within a single synapse, and on-device and parallel learning. Simulation results of statistic metrics and classification tasks on several real-world datasets substantiate the validity of MSP.

Department(s)

Electrical and Computer Engineering

Second Department

Computer Science

Research Center/Lab(s)

Center for High Performance Computing Research

Second Research Center/Lab

Intelligent Systems Center

Publication Status

Early Access

Keywords and Phrases

Hierarchical Temporal Memory (HTM); Intelligent Control; Memristor; Memristors; Neural Networks; Neuromorphic Architecture; Resistance; Spatial Pooler (SP); Synapses; Task Analysis; Threshold Voltage; Training

International Standard Serial Number (ISSN)

2168-2216; 2168-2232

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2020 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

03 Dec 2020

Link to Full Text

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