Race Conditions among Protection Devices for a High Speed I/O Interface
The ESD coupling path and on-board impedances strongly affect the ESD rise time seen on a PCB trace. Possible race conditions between external and on-die ESD protection were studied using measurement-based models of the transient response and on-board passives. Results show the interplay of rise time and protection turn-on can prevent the external TVS from responding in time.
J. Zhou et al., "Race Conditions among Protection Devices for a High Speed I/O Interface," Proceedings of the 42nd Annual Electrical Overstress/Electrostatic Discharge Symposium (2020, Reno, NV), pp. 1 - 6, Institute of Electrical and Electronics Engineers (IEEE), Nov 2020.
42nd Annual EOS/ESD Symposium (2020: Sep. 13-18, Reno, NV)
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
International Standard Book Number (ISBN)
International Standard Serial Number (ISSN)
Article - Conference proceedings
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10 Nov 2020