Far-End Crosstalk Mitigation for Microstrip Lines in High-Speed PCBs
Abstract
With improvement in the speed and frequency of electronic circuits, far-end crosstalk (FEXT) problem in printed-circuit board (PCB) neighboring routes becomes one of most critical factors affecting signal quality. In this paper, the FEXT can be mitigated significantly by inserting rectangular-shape resonators (RSR) structures in the coupled microstrip transmission lines where defected microstrip structures (DMS) are etched on the lines. The frequency domain simulation of HFSS shows that the S41 of this proposed structure is decreased more than 16dB around 3.2GHz, compared with the traditional signal routing. The time domain simulation of ADS shows that the peak of FEXT voltage of this structure is improved to 89% compared to the traditional signal routing. It has been successfully demonstrated by simulation and comparison with all previous techniques that, this novel technique gives the best optimum low values for the peak voltage of FEXT. Thus, there is a great potential in DDR5, where the requirement of the high density wiring design is even severe.
Recommended Citation
L. Zhang et al., "Far-End Crosstalk Mitigation for Microstrip Lines in High-Speed PCBs," Proceedings of the 2019 Cross Strait Quad-Regional Radio Science and Wireless Technology Conference (2019, Taiyuan, China), Institute of Electrical and Electronics Engineers (IEEE), Jul 2019.
The definitive version is available at https://doi.org/10.1109/CSQRWC.2019.8799209
Meeting Name
2019 Cross Strait Quad-Regional Radio Science and Wireless Technology Conference, CSQRWC 2019 (2019: Jul. 18-19, Taiyuan, China)
Department(s)
Electrical and Computer Engineering
Research Center/Lab(s)
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
DDR5; Defected Microstrip Structures (DMS); Far-End Crosstalk (FEXT); High-Density PCBs; Mitigation
International Standard Book Number (ISBN)
978-172811372-2
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2019 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Jul 2019
Comments
This work is supported by Intel Corporation.