The Influence of Anti-Pad Array on the Inductance of PCB Power Net Area Fill
Abstract
A low impedance power distribution network (PDN) is essential for the functionality of high speed printed circuit boards. A pre-layout impedance calculation can avoid time consuming changes on the design during post-layout stage. Design curves for inductance estimation are convenient to use in pre-layout stage. However, the high density voids on the power plane, which is caused by the anti-pads, are not considered in those design curves. This short paper discussed the extra inductance caused by the anti-pads, in two common situations.
Recommended Citation
Q. Sun et al., "The Influence of Anti-Pad Array on the Inductance of PCB Power Net Area Fill," Proceedings of the 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (2017, Haining, China), Institute of Electrical and Electronics Engineers (IEEE), Dec 2017.
The definitive version is available at https://doi.org/10.1109/EDAPS.2017.8277012
Meeting Name
2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium, EDAPS 2017 (2017: Dec. 14-16, Haining, China)
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Inductance; Design curves; Impedance calculations; Inductance estimations; Low impedance; Plane-pair PEEC; Power distribution network; Power integrity; Power planes; Printed circuit boards
International Standard Book Number (ISBN)
978-1-5386-1238-5
International Standard Serial Number (ISSN)
2151-1233
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2017 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Dec 2017
