PCB Edge Shielding Effectiveness Evaluation and Design Guidelines
Abstract
Edge plating and via stitching connecting ground planes are two common edge treatments to suppress electromagnetic interference (EMI) from multilayer printed circuit boards (PCB). One critical parameter for stitching via is the spacing between vias. At higher frequencies, it is desirable to plate the edges of PCB, and a gap is required in the plating to accommodate the break-off tabs. In this paper, the shielding performance of these two scenarios are studied in both simulation and measurement. By sweeping the parameters of via pitch size and the length of each plated edge, the near-field shielding effectiveness (SE) of these different cases are compared. In general, the edge plating cases have much better shielding performance than the stitching via ones. Since edge plating implements the shielding on PCB walls, it leaves no interference with signals and moreover saves space for dropping GND stitching vias, with a trade-off of 5% more cost. Design guidelines for PCB edge treatments are provided in the end of the paper.
Recommended Citation
Y. S. Cao et al., "PCB Edge Shielding Effectiveness Evaluation and Design Guidelines," Proceedings of the 2018 IEEE Symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity (2018, Long Beach, CA), pp. 269 - 274, Institute of Electrical and Electronics Engineers (IEEE), Jul 2018.
The definitive version is available at https://doi.org/10.1109/EMCSI.2018.8495380
Meeting Name
2018 IEEE Symposium on Electromagnetic Compatibility, Signal Integrity and Power Integrity, EMC, SI and PI 2018 (2018: Jul. 30-Aug. 3, Long Beach, CA)
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Busbars; Design; Economic and social effects; Electromagnetic compatibility; Electromagnetic pulse; Electromagnetic shielding; Magnetic shielding; Plating; Ground planes; Higher frequencies; Multilayer printed circuit board; Near fields; Shielding effectiveness; Shielding performance; Simulations and measurements; Trade off; Printed circuit boards; Edge plating; EMI; Via stitching
International Standard Book Number (ISBN)
978-1-5386-6621-0
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2018 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Jul 2018
Comments
This material is based upon work supported by Google Inc. and the National Science Foundation under Grant No. IIP-1440110.