Through Silicon Via Time Domain Crosstalk Modeling Considering Hysteretic Coupling Capacitance
The paper deals with the time domain modeling of the hysteretic behavior of the coupling capacitance from a through silicon via (TSV). The model is developed in such a way that it can be implemented into standard circuit simulators. Results showing the effect of the hysteresis on the electrical performances of the signal channel containing the TSV are shown and discussed.
S. Piersanti et al., "Through Silicon Via Time Domain Crosstalk Modeling Considering Hysteretic Coupling Capacitance," Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (2015, Dresden, Germany), pp. 567-572, Institute of Electrical and Electronics Engineers (IEEE), Aug 2015.
The definitive version is available at https://doi.org/10.1109/ISEMC.2015.7256225
IEEE International Symposium on Electromagnetic Compatibility, EMC 2015 (2015: Aug. 16-22, Dresden, Germany)
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
circuit modeling; hysteresis; non linear effects; Through Silicon Vias; time domain modeling
International Standard Book Number (ISBN)
International Standard Serial Number (ISSN)
Article - Conference proceedings
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01 Aug 2015