Origin of Device Performance Enhancement of Junctionless Accumulation-Mode (JAM) Bulk FinFETs with High-Κ Gate Spacers
Abstract
In this letter, we investigated the junctionless accumulation-mode (JAM) bulk FinFETs with high-κ gate spacers showing enhanced device performance in SS, DIBL, and ON/OFF current ratio. We found that origin of the ON-state current enhancement was reduction of the initial energy barrier between the source and channel, and reason for the OFF-state current reduction was L G extension caused by the fringing field through high-κ gate spacers. The off-state leakage current decreased by over one order of magnitude. The ON-state current was remarkably enhanced by 180% over that of low-κ gate spacers. The high-κ gate spacer is indispensable for enhancing the performance of the JAM field-effect transistor in a sub 20-nm -gate length regime.
Recommended Citation
J. H. Choi et al., "Origin of Device Performance Enhancement of Junctionless Accumulation-Mode (JAM) Bulk FinFETs with High-Κ Gate Spacers," IEEE Electron Device Letters, vol. 35, no. 12, pp. 1182 - 1184, Institute of Electrical and Electronics Engineers (IEEE), Dec 2014.
The definitive version is available at https://doi.org/10.1109/LED.2014.2364093
Department(s)
Electrical and Computer Engineering
Research Center/Lab(s)
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
fringing field; high-k gate spacers; JAM FET
International Standard Serial Number (ISSN)
0741-3106
Document Type
Article - Journal
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2014 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Dec 2014
