Detection of Open and Short Faults in 3D-ICs based on Through Silicon Via (TSV)
This paper proposes a procedure for estimating the location of open or short defects in a Through Silicon Via daisy-chain structure. The equivalent inductance and capacitance are extracted, at low frequency, through the measured and/or computed Z11 parameter of a three dimensional model in which the short and open defects are intentionally created in specific points.
S. Piersanti et al., "Detection of Open and Short Faults in 3D-ICs based on Through Silicon Via (TSV)," Proceedings of the 2017 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (2017, Washington, DC), pp. 405-410, Institute of Electrical and Electronics Engineers (IEEE), Aug 2017.
The definitive version is available at https://doi.org/10.1109/ISEMC.2017.8077904
2017 IEEE International Symposium on Electromagnetic Compatibility, EMCSI (2017: Aug. 7-11, Washington, DC)
Electrical and Computer Engineering
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Defects; Electromagnetic compatibility; Electronics packaging; Fault detection; Integrated circuit interconnects; Integrated circuit manufacture; Timing circuits; Circuit defect; Daisy chain structure; Equivalent inductance; Low-frequency; Open circuits; Three-dimensional model; Through-Silicon-Via (TSV); Three dimensional integrated circuits; 3D-IC; Open circuit defect; Short circuit defect
International Standard Book Number (ISBN)
International Standard Serial Number (ISSN)
Article - Conference proceedings
© 2017 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Aug 2017