Detection of Open and Short Faults in 3D-ICs based on Through Silicon Via (TSV)

Abstract

This paper proposes a procedure for estimating the location of open or short defects in a Through Silicon Via daisy-chain structure. The equivalent inductance and capacitance are extracted, at low frequency, through the measured and/or computed Z11 parameter of a three dimensional model in which the short and open defects are intentionally created in specific points.

Meeting Name

2017 IEEE International Symposium on Electromagnetic Compatibility, EMCSI (2017: Aug. 7-11, Washington, DC)

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Defects; Electromagnetic compatibility; Electronics packaging; Fault detection; Integrated circuit interconnects; Integrated circuit manufacture; Timing circuits; Circuit defect; Daisy chain structure; Equivalent inductance; Low-frequency; Open circuits; Three-dimensional model; Through-Silicon-Via (TSV); Three dimensional integrated circuits; 3D-IC; Open circuit defect; Short circuit defect

International Standard Book Number (ISBN)

978-1-5386-2229-2

International Standard Serial Number (ISSN)

1077-4076; 2158-1118

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2017 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Aug 2017

Link to Full Text

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