Dynamic Yield Analysis and Enhancement of FPGA Reconfigurable Memory System
Abstract
This paper discusses the issues of FPGA reconfigurable memory system with faulty physical memory cells and yield measurement techniques are proposed. Static yield and dynamic yield of FPGA reconfigurable memory systems and their characteristics are analyzed. Yield enhancement of conventional memory systems relies on additional redundancy, but FPGA reconfigurable memory systems have inherited redundancy and customizability. Thus, they can accommodate numerous target memory configurations and redundant memory cells, if any, can be used as spares to enhance dynamic yield of the target memory configuration. Three fundamental strategies are introduced and analyzed: redundant bits, redundant words and combination of both. Mathematical analysis of those techniques also has been conducted to clarify their effects on yield. Selecting the most yield enhancing logical memory configuration which can accommodate the given target memory requirement among candidate configurations is referred to as optimal fitting. Optimal fitting algorithms for single configuration fitting, sequential reconfiguration system (SRS) fitting and concurrent reconfiguration system (CRS) fitting are proposed and analyzed based on the yield analysis techniques.
Recommended Citation
M. Choi and N. Park, "Dynamic Yield Analysis and Enhancement of FPGA Reconfigurable Memory System," Proceedings of the 18th IEEE Instrumentation and Technology Conference: Rediscovering Measurement in the Age of Informatics (2001, Budapest, Hungary), vol. 1, pp. 386 - 391, Institute of Electrical and Electronics Engineers (IEEE), May 2001.
The definitive version is available at https://doi.org/10.1109/IMTC.2001.928845
Meeting Name
18th IEEE Instrumentation and Technology Conference: IMTC: Rediscovering Measurement in the Age of Informatics (2001: May 21-23, Budapest, Hungary)
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Algorithms; Computer Aided Software Engineering; Digital Storage; Embedded Systems; Logic Design; Concurrent Reconfiguration System; Logical Memory; Reconfigurable Memory System; Sequential Reconfiguration System; Field Programmable Gate Arrays (FPGA); Concurrent Reconfiguration; Dynamic Yield; FPGA-Based Instrumentation; Memory Yield Enhancement; Memory Yield Measurement; Optimal Fitting; Reconfigurable Memory; Sequential Reconfiguration; Static Yield
International Standard Book Number (ISBN)
780366468
International Standard Serial Number (ISSN)
1091-5281
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2001 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 May 2001
