A Novel "Divide and Conquer" Testing Technique for Memristor Based Lookup Table

Abstract

The recently proposed nanoscale asynchronous crossbar architecture based on memristor-based look up table (MLUT) combines the advantages of memristor technology and asynchronous design for viable nanoscale computing. In spite of having numerous merits over the clocked counterparts and previous asynchronous designs, it is bound to have inevitable defects due to nondeterministic nanoscale assembly. In order to assess the reliability of MLUT, there is a need to develop efficient testing techniques. Typical approach so far has been to test every crosspoint on each crossbar MLUT exhaustively; this is not only tedious but is also prohibitively time consuming for designs involving large number of MLUTs. This paper introduces a novel testing scheme based on "Divide and Conquer" approach to efficiently locate the defective memristors in a MLUT. The proposed testing scheme leverages upon a special current additive property of the memristor based multiplexer. It performs binary isolation of regions, reducing the search space by half whenever applicable. Numerical simulations clearly demonstrate that the approach is generic, deterministic, and scalable.

Meeting Name

IEEE 54th International Midwest Symposium on Circuits and Systems: MWSCAS (2011: Aug. 7-10, Seoul, South Korea)

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Asynchronous Design; Crossbar Architecture; Divide and Conquer; Look up Table; Memristor; Nano Scale; Nanoscale Assemblies; Novel Testing; Search Spaces; Testing Technique; Asynchronous Sequential Logic; Design; Nanostructured Materials; Nanotechnology; Passive Filters; Resistors; Table Lookup; Testing; Memristors

International Standard Book Number (ISBN)

978-1612848570; 978-1612848563

International Standard Serial Number (ISSN)

1548-3746; 1558-3899

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2011 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Aug 2011

Link to Full Text

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