A High Speed Low Power Modulo 2ⁿ + 1 Multiplier Design using Carbon-Nanotube Technology
Abstract
Modulo 2n + 1 multiplier is one of the critical components in the area of digital signal processing, residue arithmetic, and data encryption that demand high-speed and low-power operation. In this paper, a new circuit implementation of a high-speed low-power modulo 2n + 1 multiplier is proposed. It has three major stages: partial product generation stage, partial product reduction stage, and the final adder stage. The proposed structure introduces a new MUX-based compressor in the partial product reduction stage to reduce power and increase speed, and in the final adder stage, the Sparse-tree-based inverted end-around-carry adder reduces the number of critical path circuit blocks, also avoids wire interconnection problem. The proposed multiplier is implemented using both 32nm CNTFET (Carbon-Nanotube FET) and bulk CMOS technology for performance comparison. The CNTFET-based design dramatically decreases the PDP (Power Delay Product) of the circuit. The simulation results demonstrate that the power consumption of CNTFET-based multiplier is at average 5.72 times less than its CMOS counterpart, while the PDP of CNTFET is 94 times less than the CMOS one.
Recommended Citation
H. Qi et al., "A High Speed Low Power Modulo 2ⁿ + 1 Multiplier Design using Carbon-Nanotube Technology," Proceedings of the IEEE 55th International Midwest Symposium on Circuits and Systems (2012, Boise, ID), pp. 406 - 409, Institute of Electrical and Electronics Engineers (IEEE), Aug 2012.
The definitive version is available at https://doi.org/10.1109/MWSCAS.2012.6292043
Meeting Name
IEEE 55th International Midwest Symposium on Circuits and Systems: MWSCAS (2012: Aug. 5-8, Boise, ID)
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Bulk CMOS; Circuit Blocks; Circuit Implementation; Critical Component; Critical Paths; Data Encryption; High-Speed; Low Power; Low-Power Operation; Modulo 2; Multiplier Design; MUX-based; Partial Product; Partial Product Reduction; Performance Comparison; Power Delay Product; Residue Arithmetic; Wire Interconnections; Adders; Carbon; CMOS Integrated Circuits; Digital Signal Processing; Multiplying Circuits; Product Design; Low Power Electronics
International Standard Book Number (ISBN)
978-1467325264; 978-1467325271
International Standard Serial Number (ISSN)
1548-3746; 1558-3899
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2012 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Aug 2012
