Time Domain PDN Noise Modeling for High Performance System

Abstract

In this paper, we investigate the impact of the PDN inductance/impedance as well as the decoupling capacitors location on the initial IC noise voltage drop for a high performance system. To consider a worst case situation for the noise voltage at the integrated circuit (IC) we set the on-chip capacitance to zero. The impact of the delay due to remote location of the decoupling capacitors for fast rise-time current waveforms is also studied.

Meeting Name

25th IEEE Conference on Electrical Performance of Electronic Packaging and Systems (2016: Oct. 23-26, San Diego, CA)

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Capacitance; Electronics Packaging; Decoupling Capacitor; Fast Rise Time; High Performance Systems; On-Chip Capacitance; Power Distribution Modeling; Power Integrity; PPP Solver; Remote Location; Integrated Circuits; Power Integrity Analysis; Capacitors; Inductance; Time-Domain Analysis; Delays; Impedance; Pins; Waveform Analysis; Electric Impedance; Inductance; Integrated Circuit Interconnections; Integrated Circuit Noise; Power Integrated Circuits; Rise-Time Current Waveforms; Time Domain PDN Noise Modeling; High Performance System; PDN Inductance Impact; PDN Impedance Impact; Decoupling Capacitor Location; IC Noise Voltage Drop; Noise Voltage; Delay Impact

International Standard Book Number (ISBN)

978-1509061105; 978-1509022724

International Standard Serial Number (ISSN)

2165-4115

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2016 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Oct 2016

Link to Full Text

Share

 
COinS