Design and Implementation of an FPGA-based Processor for Compressed Images
This paper deals with the implementation of a systolic array architecture in hardware using FPGAs for processing compressed binary images without decompressing them. Specifically, run-length encoding (RLE) is used for compression. Processing images in compressed form provides a significant speedup in the computation. Using a systolic architecture and implementing it in hardware further increases the speed.
V. S. Balakrishnan et al., "Design and Implementation of an FPGA-based Processor for Compressed Images," Proceedings of SPIE International Conference on Parallel and Distributed Methods for Image Processing IV, SPIE -- The International Society for Optical Engineering, Jul 2000.
The definitive version is available at https://doi.org/10.1117/12.403594
Electrical and Computer Engineering
Keywords and Phrases
Binary Images; Image Coding; Image Compression; Microprocessor Chips
Article - Conference proceedings
© 2000 SPIE -- The International Society for Optical Engineering, All rights reserved.
01 Jul 2000