Effect of Narrow Power Fills on PCB PDN Noise

Abstract

The printed circuit board (PCB) power delivery network (PDN) performance has become critical with the reducing margins on power noise. This paper deals with a specific question about the size of the power area fill used to route the power current from the dc regulator to integrated circuit(IC), and also used for connecting to the decoupling capacitors. With increased PCB real estate costs, narrow power fills are required, which results in an increase in the connection inductance of decoupling capacitors. This paper uses a proven lumped circuit model extraction procedure, based on the first principle resonant cavity model, to demonstrate the effect of narrow and wide area fills used in typical PCB PDN designs. The frequency domain results thus obtained are used with typical IC current draw profiles to show the impact on the noise voltage developed at the IC. Some design guidelines and conclusions are drawn from these results.

Meeting Name

2014 IEEE International Symposium on Electromagnetic Compatibility (2014: Aug. 4-8, Raleigh, NC)

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Center for High Performance Computing Research

Second Research Center/Lab

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Capacitors; Electric power transmission; Electromagnetic compatibility; Frequency domain analysis; Lumped parameter networks; Paper capacitors; Printed circuits; Decoupling capacitor; First principles; Frequency domains; Lumped circuit models; PDN noise; Power delivery network (PDN); Power Distribution Network Design; Printed circuit boards (PCB); Printed circuit boards; Narrow area fills

International Standard Serial Number (ISSN)

1077-4076

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2014 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

08 Aug 2014

Link to Full Text

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