Conducted-Emission Modeling for a High-Speed ECL Clock Buffer
Total voltage sources and Thevenin equivalent circuits are derived by measurements and simulations using IBIS models to characterize the conducted emissions from ICs. The constructed noise source model for a test IC is applied in systemlevel simulations and the calculated far field radiation is validated with measurements. The agreement between simulated and measured results demonstrates the effectiveness of the constructed model for characterizing the conducted emissions from an IC's I/O pins.
S. Jin et al., "Conducted-Emission Modeling for a High-Speed ECL Clock Buffer," Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (2014, Raleigh, NC), pp. 594-599, Institute of Electrical and Electronics Engineers (IEEE), Aug 2014.
The definitive version is available at https://doi.org/10.1109/ISEMC.2014.6899040
2014 IEEE International Symposium on Electromagnetic Compatibility (2014: Aug. 4-8, Raleigh, NC)
Electrical and Computer Engineering
Center for High Performance Computing Research
Second Research Center/Lab
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Equivalent circuits; Clock buffer; Conducted emissions; Far-field radiation; Measured results; Noise source models; System level simulation; Thevenin equivalent circuit; Voltage source; Electromagnetic compatibility
International Standard Serial Number (ISSN)
Article - Conference proceedings
© 2014 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
08 Aug 2014