Modeling Shared-Via Decoupling in a Multi-Layer Structure Using the CEMPIE Approach
Abstract
The CEMPIE approach, a circuit extraction technique based on a mixed-potential integral equation, has been applied to model multi-layer structures including power and signal layers. Power-bus noise mitigation effects due to a decoupling capacitor were studied for several cases with different spacing between the capacitor and an integrated circuit (IC). Modeling results indicate that the capacitor sharing a common via with the IC power/ground pins is superior; viz., it results in the lowest power-bus noise under similar conditions.
Recommended Citation
W. Cui et al., "Modeling Shared-Via Decoupling in a Multi-Layer Structure Using the CEMPIE Approach," Proceedings of the IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (2001, Cambridge, MA), pp. 265 - 268, Institute of Electrical and Electronics Engineers (IEEE), Oct 2001.
The definitive version is available at https://doi.org/10.1109/EPEP.2001.967660
Meeting Name
IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (2001: Oct. 22-31, Cambridge, MA)
Department(s)
Electrical and Computer Engineering
Research Center/Lab(s)
Electromagnetic Compatibility (EMC) Laboratory
Keywords and Phrases
Circuit Simulation; Equivalent Circuits; High-Speed Integrated Circuits; Integrated Circuit Modelling; Integrated Circuit Noise; Power Supply Circuits; Integral Equations; Integrated Circuit Layout; Interconnection Networks; Mathematical Models; Surface Mount Technology; Circuit Extraction Technique; Partial Element Equivalent Circuits; Electric Network Analysis
International Standard Book Number (ISBN)
780370244
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2001 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Oct 2001
