Formulation and Network Model Reduction for Analysis of the Power Distribution Network in a Production-Level Multilayered Printed Circuit Board

Abstract

A methodology for modeling the power delivery network from the voltage regulator module to the pins of a high pin count integrated circuit on a printed circuit board (PCB) is presented. The proposed model is based on inductance extraction from first principle formulation of a cavity formed by parallel metal planes. Circuit reduction is used to practically realize the model for a production level, complex, multilayer PCBs. The lumped element model is compatible with SPICE-type simulators. The resulting model has a relatively simple circuit topology. The model is corroborated with microprobing measurements up to a few gigahertz. The model can be used for a wide range of geometry variations in a power integrity analysis, including complex power/ground stack up, various numbers of decoupling capacitors with arbitrary locations, numerous IC power pins and IC power/ground return via layouts, as well as hundreds of ground return vias.

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Center for High Performance Computing Research

Second Research Center/Lab

Electromagnetic Compatibility (EMC) Laboratory

Keywords and Phrases

Complex networks; Electric network analysis; Electric power transmission; Printed circuits; Reconfigurable hardware; Topology; Voltage regulators; Decoupling capacitor; Inductance extraction; Lumped element model; Multi-layered printed circuit boards; Power delivery network; Power distribution network; Printed circuit boards (PCB); Voltage regulator module; Printed circuit boards; Modeling PCB PDN; power integrity

International Standard Serial Number (ISSN)

0018-9375

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2016 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Jun 2016

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