Abstract

In this paper, a new architecture of distributed embedded memory cores for SoC is proposed and an effective memory repair method by using the proposed Spare Line Borrowing (software-driven reconfiguration) technique is investigated. It is known that faulty cells in memory core show spatial locality, also known as fault clustering. This physical phenomenon tends to occur more often as deep submicron technology advances due to defects that span multiple circuit elements and sophisticated circuit design. The combination of new architecture & repair method proposed in this paper ensures fault tolerance enhancement in SoC, especially in case of fault clustering. This fault tolerance enhancement is obtained through optimal redundancy utilization: Spare redundancy in a fault-resistant memory core is used to fix the fault in a fault-prone memory core. The effect of Spare Line Borrowing technique on the reliability of distributed memory cores is analyzed through modeling and extensive parametic simulation.

Meeting Name

IEEE Instrumentation and Measurement Technology Conference: IMTC (2005: May 16-19, Ottawa, Canada)

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Memory Repair; Reconfiguration; System-On-A-Chip (SoC); Spare Line Borrowing Technique; Computer Architecture; Computer Software; Distributed Computer Systems; Fault Tolerant Computer Systems; Storage Allocation (Computer); Embedded Systems

International Standard Book Number (ISBN)

978-0780388796

International Standard Serial Number (ISSN)

1091-5281

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 2005 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 May 2005

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