Abstract

There have been numerous nanowire crossbar architectures proposed till date, although all of them are envisioned to be synchronous (i.e., clocked). The clock is an important part in a circuit and it needs to be connected to all the components to synchronize their operation. Considering non-deterministic nature of nanoscale integration, realizing them on a nano wire crossbar system would be quite cumbersome. Unlike the conventional clocked counterparts, a new clock-free crossbar architecture is proposed to resolve the issues with clocked counterparts in this paper, where the use of clock is eliminated from the architecture. This has been done by implementing delay-insensitive logic encoding technique called Null Convention Logic (NCL). A delay-insensitive full adder has been implemented on the proposed architecture to demonstrate the feasibility in this paper.

Meeting Name

7th IEEE International Conference on Nanotechnology: IEEE-NANO (2007: Aug. 2-5, Hong Kong, China)

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Asynchronous Computing; Defect & Fault-Tolerance; Manufacturability; Nanowire Crossbar; Null Convention Logic (NCL); Robustness; Scalability; Adders; Clocks; Differentiating Circuits; Electric Wire; Nanostructured Materials; Nanostructures; Nanotechnology; Nanowires; Technology; Crossbar Architecture; Full Adder; International Conferences; Manufacturability; Nanoscale Integration; Proposed Architectures; Architecture

International Standard Book Number (ISBN)

978-1424406074

International Standard Serial Number (ISSN)

1944-9399

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 2007 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 Aug 2007

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