Abstract
In this paper, a two-dimensional (2D) Crank-Nicholason (CN) finite difference time domain (FDTD) method is proposed for VLSI interconnect/substrate characterization. Through rigorous truncation and dispersion error analyses, a guideline on using this technique is presented. Several iterative solvers are investigated to accelerate the solution of the CN-FDTD scheme. Numerical examples are given to demonstrate the accuracy and the efficiency of the proposed algorithm.
Recommended Citation
R. Qiang et al., "A CN-FDTD Scheme and Its Application to VLSI Interconnects/Substrate Modeling," Proceedings of the IEEE International Symposium on Electromagnetic Compatibility (2004, Santa Clara, CA), vol. 1, pp. 97 - 101, Institute of Electrical and Electronics Engineers (IEEE), Aug 2004.
The definitive version is available at https://doi.org/10.1109/ISEMC.2004.1350004
Meeting Name
IEEE International Symposium on Electromagnetic Compatibility (2004: Aug. 9-13, Santa Clara, CA)
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
2D FDTD Method; CN-FDTD Scheme; Crank-Nicholason Method; VLSI; VLSI Interconnect/Substrate Characterization; Dispersion Error Analysis; Finite Difference Time Domain Method; Finite Difference Time-Domain Analysis; Integrated Circuit Interconnections; Integrated Circuit Modelling; Iterative Methods; Iterative Solvers; Truncation Error Analysis; Two-Dimensional FDTD Method; Very Large Scale Integration; Finite Difference Methods; Time Domain Analysis; Finite Wordlength Effects; Error Analysis; Magnetic Analysis; Iterative Algorithms; Equations
International Standard Book Number (ISBN)
780384431
International Standard Serial Number (ISSN)
1077-4076
Document Type
Article - Conference proceedings
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2004 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Aug 2004
