Abstract
Via interconnects in multilayer substrates, such as chip scale packaging, ball grid arrays, multichip modules, and printed circuit boards (PCB) can critically impact system performance. Lumped-circuit models for vias are usually established from their geometries to better understand the physics. This paper presents a procedure to extract these element values from a partial element equivalent circuit type method, denoted by CEMPIE. With a known physics-based circuit prototype, this approach calculates the element values from an extensive circuit net extracted by the CEMPIE method. Via inductances in a PCB power bus, including mutual inductances if multiple vias are present, are extracted in a systematic manner using this approach. A closed-form expression for via self inductance is further derived as a function of power plane dimensions, via diameter, power/ground layer separation, and via location. The expression can be used in practical designs for evaluating via inductance without the necessity of full-wave modeling, and, predicting power-bus impedance as well as effective frequency range of decoupling capacitors.
Recommended Citation
J. Fan et al., "Lumped-Circuit Model Extraction for Vias in Multilayer Substrates," IEEE Transactions on Electromagnetic Compatibility, vol. 45, no. 2, pp. 272 - 280, Institute of Electrical and Electronics Engineers (IEEE), May 2003.
The definitive version is available at https://doi.org/10.1109/TEMC.2003.810808
Department(s)
Electrical and Computer Engineering
Research Center/Lab(s)
Electromagnetic Compatibility (EMC) Laboratory
Sponsor(s)
United States. Army Research Office
Keywords and Phrases
CEMPIE; Ball Grid Arrays; Chip Scale Packaging; Closed-Form Expression; Decoupling Capacitors; Effective Frequency Range; Element Values; Equivalent Circuits; Full-Wave Modeling; Geometries; Inductance; Lumped-Circuit Model Extraction; Multichip Modules; Multilayer Substrates; Mutual Inductances; Partial Element Equivalent Circuit Type Method; Physics-Based Circuit Prototype; Power Plane Dimensions; Power-Bus Impedance; Power/Ground Layer Separation; Printed Circuit Boards; Printed Circuit Design; Self Inductance; Surface Mount Technology; Via Diameter; Via Location; Vias; DC Power-Bus Design; Decoupling Capacitor Design; Multilayer Substrate; Via Inductance; Via Interconnects
International Standard Serial Number (ISSN)
0018-9375; 1558-187X
Document Type
Article - Journal
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2003 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 May 2003
Comments
This work was supported in part by the U.S. Army Research Office under Grant DAAG55-97-1-0001 as part of the DDR&E MURI program.