Abstract
SoCs are in general built with embedded IP cores, each of which is procured from different IP providers with no prior information on known-good-yield (KGY). In practice, partial testing is a practical choice for assuring the yield of the product under the stringent time-to-market requirements. Therefore, a proper sampling technique is a key to high confidence testing and cost effectiveness. Based on previous research, this paper proposes a novel statistical testing technique for increasingly hybrid integrated systems fabricated on a single silicon die with no a-priori empirical yield data. This problem is referred to as the unknown-good-yield (UKGY) problem. The proposed testing method, referred to as regressive testing (RegT) in this paper, exploits another way around by using parameters (referred to as assistant variables (AV)) that are employed to evaluate the yields of randomly sampled SoCs and thereby estimating the good yield by using a regression analysis method with regard to confidence intervals. Numerous simulations are conducted to demonstrate the efficiency and effectiveness of the proposed RegT in comparison to characterization-based testing methods.
Recommended Citation
N. J. Park et al., "High Confidence Testing for Instrumentation System-on-Chip with Unknown-Good-Yield," Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference (2004, Como, Italy), vol. 2, pp. 1478 - 1483, Institute of Electrical and Electronics Engineers (IEEE), May 2004.
The definitive version is available at https://doi.org/10.1109/IMTC.2004.1351346
Meeting Name
21st IEEE Instrumentation and Measurement Technology Conference: IMTC (2004: May 18-20, Como, Italy)
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
KGY; SoC High Confidence Testing; UKGY; Assistant Variable; Characterization-Based Testing Methods; Correlation Analysis; Correlation Methods; Defect Level; Embedded IP Cores; Fault Coverage; Hybrid Integrated Systems; Industrial Property; Instrumentation System-On-Chip; Integrated Circuit Testing; Integrated Circuit Yield; Known-Good-Yield; Partial Testing; Randomly Sampled SoC; Regression Analysis; Regressive Testing; Sampling Methods; Sampling Technique; Statistical Testing; Statistical Testing Technique; System-On-Chip (SoC); Unknown-Good-Yield (UKGY); Experimental Testing; Good Yield Rate (GYR)
International Standard Book Number (ISBN)
078038248X
International Standard Serial Number (ISSN)
1091-5281
Document Type
Article - Conference proceedings
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2004 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 May 2004
