A method to extract a lumped element prototype SPICE model is used to study noise coupling between non-parallel traces on a PCB. The parameters in this model are extracted using a PEEC-like approach, a Circuit Extraction approach based on a Mixed-Potential Integral Equation formulation (CEMPIE). Without large numbers of unknowns, the SPICE model saves computation time. Also, it is easy to incorporate into system SPICE net list to acquire the system simulation result considering the coupling between traces on the printed circuit board (PCB). A representative case is studied, and the comparison of measurements, CEMPIE simulation, and SPICE modeling are given.

Meeting Name

52nd IEEE Electronic Components and Technology Conference (2002: May 28-31, San Diego, CA)


Electrical and Computer Engineering

Keywords and Phrases

CAD Model; CEMPIE Simulation; PCB Layout; PEEC; SPICE; Circuit Extraction; Circuit Layout CAD; Circuit Noise; Equivalent Circuits; Integral Equations; Lumped Element SPICE Model; Mixed-Potential Integral Equation; Noise Coupling; Nonparallel Traces; Parameter Extraction; Printed Circuit Layout; Via; Computer Aided Design; Computer Simulation; Electric Lines; Mathematical Models; Matrix Algebra; Spurious Signal Noise; Quantifying Noise; Printed Circuit Boards

International Standard Book Number (ISBN)


International Standard Serial Number (ISSN)


Document Type

Article - Conference proceedings

Document Version

Final Version

File Type





© 2002 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 May 2002