Automated synthesis and NULL cycle reduction optimization for asynchronous NULL convention circuits using industry-standard CAD tools

Author

Bonita Bhaskaran

Abstract

"This dissertation focuses on developing algorithms for design automation of asynchronous NULL Convention Logic (NCL) circuits. Despite the numerous benefits of NCL circuits, such as reduced timing effort, power dissipation, and electro-magnetic interference (EMI), increased robustness, and better suitability for System-on-Chip (SoC) design, the lack of an automated design flow continues to prevent its widespread usage in the semiconductor industry. A novel circuit synthesis algorithm and an automated throughput enhancement technique have been developed and integrated into the industry-standard Mentor Graphics CAD tool suite, such that NCL circuits can be specified as high-level algorithmic descriptions and automatically synthesized and optimized, like their synchronous counterparts"--Abstract, page iv.

Advisor(s)

Smith, Scott C.

Committee Member(s)

Beetner, Daryl G.
Choi, Minsu
McCracken, Theodore E.
Wilkerson, Ralph W.
Al-Assadi, Waleed K.

Department(s)

Electrical and Computer Engineering

Degree Name

Ph. D. in Computer Engineering

Publisher

University of Missouri--Rolla

Publication Date

Spring 2007

Journal article titles appearing in thesis/dissertation

• Threshold combinational reduction automation for synthesis of dual-rail asynchronous NULL convention digital circuits from high-level VHDL descriptions
• Automated NULL cycle reduction for asynchronous NULL convention digital circuits

Pagination

ix, 70 pages

Note about bibliography

Includes bibliographical references.

Rights

© 2007 Bonita Bhaskaran, All rights reserved.

Document Type

Dissertation - Citation

File Type

text

Language

English

Subject Headings

Asynchronous circuits -- Computer-aided designLogic designLogic, Symbolic and mathematical

Thesis Number

T 9203

Print OCLC #

180702235

Recommended Citation

Bhaskaran, Bonita, "Automated synthesis and NULL cycle reduction optimization for asynchronous NULL convention circuits using industry-standard CAD tools" (2007). Doctoral Dissertations. 1730.
https://scholarsmine.mst.edu/doctoral_dissertations/1730