Abstract

The PRAM model has been shown to be an optimal design for emulating both loos and tightly coupled multiprocessors for unit time operations. Extensions to this design employ software pipelining on a network of homogeneous workstations. Partitioning array data structures and pipelining groups of partitions to processors can minimize latency and bottlenecking on distributted message passing multiprocessing architectures. Our previous paper developed a general message passing design that was conjectured to port to a CMS and scale to more processors connected via TCPIP protocol. This paper presents the results of of our ported and scaled designs. We have indeed developed a portable, scalable design for matrix reduction (which includes matrix multiply and outer product).

Department(s)

Computer Science

Comments

The second Author is a Graduate Student.The third and fourth Authors are from the Computer Science department of the University of Vermont, Burlington, VT.

Report Number

CSc-94-04

Document Type

Technical Report

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 1994 University of Missouri - Rolla, All rights reserved

Publication Date

24 January, 1994

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