MC Scheduling on Varying-Speed Processors


Most existing research on Mixed-Criticality (MC) scheduling (see [1] for a review) has focused on dealing with different WCET estimations of a single piece of code. This is typically a consequence of different tools for determining worst case execution time (WCET) bounds being more or less conservative than each other.

This narrative is now being repeated with respect to processor speeds. Modern powerful and energy-efficient processors are yielding innovations that result in varying speed during run-time. For example, [2] describes a mechanism such that late signals can be recovered by delaying the next clock tick, so that logical faults do not propagate to higher (i.e., the software) levels. In a Globally Asynchronous Locally Synchronous (GALS) circuit, local clocks can be affected by signals propagating between different synchronous modules in an asynchronous manner.

Research on such varying-speed platform may lead to better understanding of a wider range of problems. For example, in data communication of automobiles, aircrafts, or wireless sensor networks, time-sensitive data-streams must be transmitted over potentially faulty communication channels, where a high bandwidth is provided under most circumstances yet only guaranteeing a lower bandwidth.

Meeting Name

Dagstuhl Seminar 15121: Mixed Criticality on Multicore/Manycore Platforms (2015: Mar. 15-20, Wadern, Germany)


Computer Science

Keywords and Phrases

Varying-Speed Processors; Model Combination

Document Type

Article - Conference proceedings

Document Version


File Type





© 2015 Schloss Dagstuhl--Leibniz-Zentrum fuer Informatik, All rights reserved.

Publication Date

01 Mar 2015