This paper presents a cost error measurement scheme and relaxed synchronization method, for simulated annealing on a distributed memory multicomputer, which predicts the amount of cost error that an algorithm will tolerate. An adaptive error control method is developed and implemented on an Intel iPSC/2
B. M. McMillin and C. Hong, "Relaxing Synchronization in Distributed Simulated Annealing," IEEE Transactions on Parallel and Distributed Systems, Institute of Electrical and Electronics Engineers (IEEE), Jan 1995.
The definitive version is available at https://doi.org/10.1109/71.342132
Keywords and Phrases
Intel IPSC/2; Adaptive Error Control Method; Cost Error Measurement Scheme; Distributed Memory Multicomputer; Distributed Memory Systems; Distributed Simulated Annealing; Error Correction Codes; Parallel Algorithms; Relaxed Synchronization Method; Simulated Annealing; Synchronisation; Synchronization
International Standard Serial Number (ISSN)
Article - Journal
© 1995 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Jan 1995