"Static timing analysis is a key process to guarantee timing closure for modern IC designs. However, additional pessimism can significantly increase the difficulty to achieve timing closure. Common path pessimism removal (CPPR) is a prevalent step to achieve accurate timing signoff. To speed up the existing exhaustive exploration on all paths in a design, this thesis introduces a fast multi-threading timing analysis for removing common path pessimism based on block-based static timing analysis. Experimental results show that the proposed method has faster runtime in removing excess pessimism from clock paths."--Abstract, page iii.
Fan, Jun, 1971-
Electrical and Computer Engineering
M.S. in Computer Engineering
Missouri University of Science and Technology
vii, 25 pages
© 2015 Chunyu Wang, All rights reserved.
Thesis - Open Access
Library of Congress Subject Headings
Electronic OCLC #
Wang, Chunyu, "Common path pessimism removal in static timing analysis" (2015). Masters Theses. 7440.