Abstract

This paper proposes a new precise macro-modeling for leakage current in BSIM4 65nm technology considering subthreshold leakage, gate tunneling leakage, stack effect, and fanout effect. Using the accurate macro-model, a heuristic algorithm is developed to estimate the leakage power and generate input test pattern for minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The experimental result shows that the leakage power estimation using our macro-model is within 5% difference when comparing to Hspice results.

Meeting Name

IEEE Instrumentation and Measurement Technology Conference: IMTC: Synergy of Science and Technology in Measurement (2007: May 1-3, Warsaw, Poland)

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Gate Tunneling Leakage Current; Integrated Circuit Modelling; Leakage Current; Subthreshold Leakage Current; IDDQ Testing; Integrated circuits -- Testing; IDDQ; Test Pattern Generator; Circuit Theory; Computer Simulation; Electron Tunneling; Heuristic Algorithms; Mathematical Models; Power Control

International Standard Book Number (ISBN)

1424405882

International Standard Serial Number (ISSN)

1091-5281

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 2007 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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