Abstract

This paper proposes a new precise macro-modeling for leakage current in BSIM4 65nm technology considering subthreshold leakage, gate tunneling leakage, stack effect, and fanout effect. Using the accurate macro-model, a heuristic algorithm is developed to estimate the leakage power and generate input test pattern for minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The experimental result shows that the leakage power estimation using our macro-model is within 5% difference when comparing to Hspice results

Meeting Name

2007 IEEE Instrumentation & Measurement Technology Conference IMTC 2007

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Gate Tunneling Leakage Current; Integrated Circuit Modelling; Leakage Current; Subthreshold Leakage Current

Library of Congress Subject Headings

Iddq testing
Integrated circuits -- Testing

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 2007 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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