This paper proposes a new precise macro-modeling for leakage current in BSIM4 65nm technology considering subthreshold leakage, gate tunneling leakage, stack effect, and fanout effect. Using the accurate macro-model, a heuristic algorithm is developed to estimate the leakage power and generate input test pattern for minimum leakage. The algorithm applies to ISCAS85 benchmark circuits, and the results are compared with the results of Hspice. The experimental result shows that the leakage power estimation using our macro-model is within 5% difference when comparing to Hspice results.
K. K. Kim et al., "Accurate Macro-Modeling for Leakage Current for IDDQ Test," Proceedings of the IEEE Instrumentation and Measurement Technology Conference: Synergy of Science and Technology in Measurement (2007, Warsaw, Poland), Institute of Electrical and Electronics Engineers (IEEE), May 2007.
The definitive version is available at http://dx.doi.org/10.1109/IMTC.2007.379346
IEEE Instrumentation and Measurement Technology Conference: IMTC: Synergy of Science and Technology in Measurement (2007: May 1-3, Warsaw, Poland)
Electrical and Computer Engineering
Keywords and Phrases
Gate Tunneling Leakage Current; Integrated Circuit Modelling; Leakage Current; Subthreshold Leakage Current; IDDQ Testing; Integrated circuits -- Testing; IDDQ; Test Pattern Generator; Circuit Theory; Computer Simulation; Electron Tunneling; Heuristic Algorithms; Mathematical Models; Power Control
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Article - Conference proceedings
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