Abstract
Work in progress at the University of Missouri-Rolla on hardware assists for high performance computing is presented. This research consists of a novel field programmable gate array (FPGA) based reconfigurable coprocessor board (the Chameleon Coprocessor) being used to evaluate hardware architectures for speedup of array computation algorithms. These algorithms are developed using a Mathematics of Arrays (MOA). They provide a means to generate addresses for data transfers that require less data movement than more traditional algorithms. In this manner, the address generation algorithms are acting as an intelligent data prefetching mechanism or special purpose cache controller. Software implementations have been used to provide speedups on the order of 100% over classical methods to the solution of heat transfer equations on a uniprocessor. We extend these methods to application designs for the Chameleon Coprocessor.
Recommended Citation
H. J. Pottinger et al., "Hardware Assists for High Performance Computing using a Mathematics of Arrays," ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA, pp. 39 - 45, Association for Computing Machinery, Jan 1995.
The definitive version is available at https://doi.org/10.1145/201310.201316
Department(s)
Electrical and Computer Engineering
Second Department
Computer Science
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Association for Computing Machinery, All rights reserved.
Publication Date
01 Jan 1995
