With molecular-scale materials, devices and fabrication techniques recently being developed, high-density computing systems in the nanometer domain emerge. An array-based nanoarchitecture has been recently proposed based on nanowires such as carbon nanotubes (CNTs) and silicon nanowires (SiNWs). High-density nanoarray-based systems consisting of nanometer-scale elements are likely to have many imperfections; thus, defect-tolerance is considered one of the most significant challenges. In this paper we propose a probabilistic yield model for the array-based nanoarchitecture. The proposed yield model can be used (1) to accurately estimate the raw and net array densities, and (2) to design and optimize more defect and fault-tolerant systems based on the array-based nanoarchitecture. As a case study, the proposed yield model is applied to the defect-tolerant addressing scheme called h-hot addressing and simulation results are discussed.
S. Zhang et al., "Modeling Yield of Carbon-Nanotube/Silicon-Nanowire FET-Based Nanoarray Architecture with H-hot Addressing Scheme," Proceedings of the 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004, Institute of Electrical and Electronics Engineers (IEEE), Jan 2004.
The definitive version is available at http://dx.doi.org/10.1109/DFTVS.2004.1347860
19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004
Electrical and Computer Engineering
Keywords and Phrases
C; CNT; FET-Based Nanoarray Architecture; Si; SiNW; Array-Based Nanoarchitecture; Carbon Nanotubes; Circuit Simulation; Computer Architecture; Defect-Tolerance; Defect-Tolerant Addressing Scheme; Defect-Tolerant Systems; Elemental Semiconductors; Fabrication Techniques; Fault-Tolerant Systems; H-Hot Addressing Scheme; High-Density Computing Systems; Integrated Circuit Modelling; Integrated Circuit Technology; Integrated Circuit Yield; Molecular-Scale Materials; Nanoelectronics; Nanometer-Scale Elements; Nanotube Devices; Nanowires; Net Array Densities; Probabilistic Yield Model; Raw Array Densities; Silicon; Silicon Nanowires; Simulation; Yield Modeling
International Standard Serial Number (ISSN)
Article - Conference proceedings
© 2004 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.