A novel asynchronous nanowire crossbar architecture has been recently proposed by authors' research group. The proposed clock-free architecture provides numerous significant benefits over its clocked counterparts which include better manufacturability, scalability, modularity and robustness. We also proposed various gate mapping and reconfiguration algorithms for defect-tolerant programming of PGMB (programmable gate macro blocks) - which is the primary building block of the proposed architecture. These algorithms were tested by simulations and a variety of parameter values were applied to show their performance characteristics. The most important performance metric of the proposed techniques is the programmability (i.e., the ratio of successfully programmed gates to the total number of gates). However, algorithms with higher programmability should come with higher time/space requirements. In this work, we will evaluate the tradeoff between programmability and time/space requirements and suggest a way to find the most suitable algorithm with acceptable combination of programmability and time/space requirements.

Meeting Name

8th IEEE Conference on Nanotechnology, 2008


Electrical and Computer Engineering

Keywords and Phrases

Asynchronous Circuits; Logic Gates; Nanoelectronics; Nanowires

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type





© 2008 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

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