Title

Comparison of Binary and Multi-level Logic Electronics for Embedded Systems

Presenter Information

Shirly Damti

Department

Electrical and Computer Engineering

Major

Electrical and Computer Engineering

Research Advisor

Watkins, Steve Eugene, 1960-
Stanley, R. Joe

Advisor's Department

Electrical and Computer Engineering

Second Advisor's Department

Electrical and Computer Engineering

Abstract

Embedded systems are dependent on low-power, miniaturized instrumentation. Comparator circuits are common elements in applications for digital threshold detection. Target applications are dedicated control devices, sensor nodes, etc. in which hardware constraints may be most critical. Comparator circuits are selected to compare binary and multi-level logic implementations. A multi-level, memory-based logic approach is in development that offers potential benefits in power usage and size with respect to traditional binary logic systems. A multi-level digital system can reduce interconnect lines and processing components if implementation issues can be overcome. The multi-level, memory-based logic approach uses mature CMOS technology, but the transistors are used for multi-level operations and memory manipulation. Circuit layouts of quaternary and binary comparators are presented to compare the approaches. In particular, power characteristics and transistor count are examined. The potential for improved embedded systems based on the multi-level, memory-based logic is discussed.

Biography

Shirly Damti is a senior in Electrical and Computer Engineering at the Missouri University of Science and Technology. Shirly plans to obtain an M.S. and Ph.D. in Electrical Engineering degree with emphasis on optics, digital image processing, computer vision, robotics, etc. Then, she plans on conducting research in the field and contribute to the global effort in exploration and improvement of technology.

Research Category

Engineering

Presentation Type

Oral Presentation

Document Type

Presentation

Location

Turner Room

Presentation Date

11 Apr 2016, 10:00 am - 10:20 am

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Apr 11th, 10:00 AM Apr 11th, 10:20 AM

Comparison of Binary and Multi-level Logic Electronics for Embedded Systems

Turner Room

Embedded systems are dependent on low-power, miniaturized instrumentation. Comparator circuits are common elements in applications for digital threshold detection. Target applications are dedicated control devices, sensor nodes, etc. in which hardware constraints may be most critical. Comparator circuits are selected to compare binary and multi-level logic implementations. A multi-level, memory-based logic approach is in development that offers potential benefits in power usage and size with respect to traditional binary logic systems. A multi-level digital system can reduce interconnect lines and processing components if implementation issues can be overcome. The multi-level, memory-based logic approach uses mature CMOS technology, but the transistors are used for multi-level operations and memory manipulation. Circuit layouts of quaternary and binary comparators are presented to compare the approaches. In particular, power characteristics and transistor count are examined. The potential for improved embedded systems based on the multi-level, memory-based logic is discussed.