Masters Theses


"This Master’s thesis outlines the design of a completely asynchronous Field Programmable Gate Array (FPGA) for implementing NULL Convention Logic (NCL) digital circuits. The proposed design uses four Configurable Logic Blocks (CLB), each of which in turn is designed using four Logic Elements (LE) to implement NCL logic function. Each LE can be configured to function as any one of the 27 fundamental NCL gates. A Logic Element is designed by concatenating a Look-Up-Table (LUT) with a pull-up pull-down transistor chain and a hysteresis loop. The interconnections and the switch box are designed using pass transistors and SRAM. In this thesis, a 4-input Look- Up Table (LUT) based 16-gate FPGA specifically for NCL circuits was designed and successfully programmed as a dual-rail non-pipelined 4-bit NCL register. The design was first created using the schematic capture, followed by layout or the physical level designs subsequent to successful simulation. The NCL FPGA is simulated at the transistor level using the 1,8V, 180nm TSMC CMOS process.

The size of FPGAs is now more than 1 million equivalent gates, making them a viable alternative to custom design for all but the most complex processors. FPGAs are relatively low-cost and are reconfigurable, making them perfect for prototyping, as well as implementing the final design, especially for low volume production. To compete with this cheap, reconfigurable synchronous implementation, an NCL-specific FPGA is needed, such that NCL circuits can be implemented without necessitating a prohibitively expensive full-custom design"--Abstract, page iii.


Al-Assadi, Waleed K.

Committee Member(s)

Wunsch, Donald C.
Sedigh, Sahra


Electrical and Computer Engineering

Degree Name

M.S. in Computer Engineering


Missouri University of Science and Technology

Publication Date

Fall 2009


ix, 51 pages

Note about bibliography

Includes bibliographical references (pages 48-50).


© 2009 Indira Priyadarshini Dugganapally, All rights reserved.

Document Type

Thesis - Open Access

File Type




Subject Headings

Asynchronous circuits -- Design
Field programmable gate arrays -- Design
Logic design

Thesis Number

T 9571

Print OCLC #


Link to Catalog Record

Electronic access to the full-text of this document is restricted to Missouri S&T users. Otherwise, request this publication directly from Missouri S&T Library or contact your local library.