Masters Theses


“As the conventional binary MOS-based VLSI technology is reaching limitations in chip area, speed, and power, new technologies are being researched. Some such technologies relate to multi-level logic design. This thesis explores the process and benefits of applying and optimizing multi-level design techniques to an existing Gray code binary system. Specifically, the multi-level system is designed using CoreMem technology and is optimized using Indira Dugganapally’s optimization techniques.

The first step is generating the n-bit binary and quaternary truth tables for an encoder’s Gray code output and additional desired data. Then, the data for each n-bit system is arranged in multi-level CoreMem arrays. Finally, each multi-level system is optimized, and the optimized systems are compared to the unoptimized ones in terms of transistor count. The comparison of the optimized and unoptimized systems shows a significant reduction in area that increases exponentially with system complexity”--Abstract, page iii.


Watkins, Steve Eugene, 1960-

Committee Member(s)

Stanley, R. Joe
Choi, Minsu


Electrical and Computer Engineering

Degree Name

M.S. in Electrical Engineering


Missouri University of Science and Technology

Publication Date

Spring 2020


x, 85 pages

Note about bibliography

Includes bibliographic references (pages 82-84).


© 2020 Shirly Adams Gamliel, All rights reserved.

Document Type

Thesis - Open Access

File Type




Thesis Number

T 11991