Masters Theses


"One of the most important aspects of modern electronic designs is device measurement and characterization. Without device measurement and characterization, the functionality of end designs cannot be guaranteed. At the silicon level (on-wafer), extracting the electrical performance of devices and structures has grown increasingly more complex with the continual shrink of feature sizes. Compared to the overall measurement setup (VNA, cables, probes, interposers, etc.), the ultra small size of on-wafer structures leads to their electrical performance being easily overshadowed by other, larger fixtures. Thus, many scientists and engineers have worked to devise ever more accurate calibration and de-embedding techniques for measurement setups. This thesis explores current state-of-the-art de-embedding techniques for both silicon transmission lines and general devices under test (DUTs). A complete evaluation is performed on several techniques, leading to a best choice selection for use in de-embedding through-silicon-vias (TSVs). During the evaluation a more intuitive approach (utilizing scattering parameters) is taken to verify the accuracy of the various de-embedding techniques. Attempts at formulating new de-embedding techniques are also explored"--Abstract, page iii.


Fan, Jun, 1971-

Committee Member(s)

Beetner, Daryl G.
Shi, Yiyu


Electrical and Computer Engineering

Degree Name

M.S. in Computer Engineering


Cisco Systems, Inc.


Missouri University of Science and Technology

Publication Date

Fall 2013


vii, 43 pages

Note about bibliography

Includes bibliographical references (pages 29-30).


© 2013 Nicholas Garrett Erickson, All rights reserved.

Document Type

Thesis - Open Access

File Type




Subject Headings

Interconnects (Integrated circuit technology) -- Design and construction
Three-dimensional integrated circuits
Embedded computer systems
Systems on a chip

Thesis Number

T 10389

Electronic OCLC #