Masters Theses

Keywords and Phrases

Programmable gate macro block (PGMB)


"With the recent development of nanoscale materials and assembly techniques, it is envisioned to build high-density reconfigurable systems which have never been achieved by the photolithography. Various reconfigurable architectures have been proposed based on nanowire crossbar structure as the primitive building block. Unfortunately, high density systems consisting of nanometer-scale elements are likely to have many imperfections and variations thus, defect-tolerance is considered as one of the most exigent challenges. Thus the defects should be located when tested and the logic has to be rerouted around them to maintain proper functionality. The thesis is organized into three papers, as described below

The first two papers evaluate three different logic mapping algorithms with defect avoidance to circumvent clustered defective cross points in nanowire reconfigurable crossbar architectures. The effectiveness of inherited redundancy and configurability utilization is demonstrated through extensive parametric simulations.

The third paper discusses programming asynchronous nano crossbar architecture and demonstrates a method to find an optimal solution to the dimensions of proposed architecture through simulations"--Abstract, page iv.


Choi, Minsu

Committee Member(s)

Ali, Shoukat
McCracken, Theodore E.


Electrical and Computer Engineering

Degree Name

M.S. in Computer Engineering


University of Missouri--Rolla

Publication Date

Spring 2007

Journal article titles appearing in thesis/dissertation

  • Inherited redundancy and configurability utilization for repairing nanowire crossbars with clustered defects
  • Cost-driven repairability optimization for nanowire crossbar architecture
  • Programming asynchronous nano crossbar architecture


viii, 63 pages

Note about bibliography

Includes bibliographical references.


© 2007 Yadunandana Yellambalase, All rights reserved.

Document Type

Thesis - Restricted Access

File Type




Subject Headings

Asynchronous circuits
Computer architecture
Logic design

Thesis Number

T 9158

Print OCLC #


Link to Catalog Record

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