Masters Theses


Fault modeling and testability of domino CMOS logic


"Domino CMOS circuits are widely used in high performance integrated circuits due to their advantages of speed, area, and power consumption over other logic families. However, testing of domino circuits is an area which still requires considerable attention. In this thesis two aspects of testing domino circuits are investigated. First, the effectiveness of popular fault models in detecting defects in domino circuits is studied. A design-for-test scheme targeted towards undetected faults is proposed and the feasibility of the scheme is proven. The second aspect that is examined is crosstalk due to capacitive circuit noise immunity in terms of signal switching speed and coupling capacitance. The validity of the model is demonstrated using SPICE simulations"--Abstract, page iii.


Electrical and Computer Engineering

Degree Name

M.S. in Computer Engineering


University of Missouri--Rolla

Publication Date

Spring 2006


ix, 57 pages


© 2006 Pavankumar Chandrasekhar, All rights reserved.

Document Type

Thesis - Citation

File Type




Subject Headings

Fault-tolerant computing
Metal oxide semiconductors, Complementary
Electronic circuits -- Noise
Crosstalk -- Prevention

Thesis Number

T 9309

Print OCLC #


Link to Catalog Record

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