Masters Theses
Abstract
"Domino CMOS circuits are widely used in high performance integrated circuits due to their advantages of speed, area, and power consumption over other logic families. However, testing of domino circuits is an area which still requires considerable attention. In this thesis two aspects of testing domino circuits are investigated. First, the effectiveness of popular fault models in detecting defects in domino circuits is studied. A design-for-test scheme targeted towards undetected faults is proposed and the feasibility of the scheme is proven. The second aspect that is examined is crosstalk due to capacitive circuit noise immunity in terms of signal switching speed and coupling capacitance. The validity of the model is demonstrated using SPICE simulations"--Abstract, page iii.
Advisor(s)
Waleed Al-Assadi
Committee Member(s)
Scott C. Smith
Minsu Choi
Shoukat Ali
Department(s)
Electrical and Computer Engineering
Degree Name
M.S. in Computer Engineering
Publisher
University of Missouri--Rolla
Publication Date
Spring 2006
Pagination
ix, 57 pages
Note about bibliography
includes bibliographical references (pages 54-56)
Rights
© 2006 Pavankumar Chandrasekhar, All rights reserved.
Document Type
Thesis - Restricted Access
File Type
text
Language
English
Subject Headings
Fault-tolerant computing
Metal oxide semiconductors, Complementary
Electronic circuits -- Noise
Crosstalk -- Prevention
Thesis Number
T 9309
Print OCLC #
237055425
Recommended Citation
Chandrasekhar, Pavankumar, "Fault modeling and testability of domino CMOS logic" (2006). Masters Theses. 5864.
https://scholarsmine.mst.edu/masters_theses/5864
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