Masters Theses


"The Advanced Encryption Standard (AES) is the most widely used symmetric key algorithm standard in different security protocols. The AES was very reliable in providing security for data until a few years ago, when researchers proved the Side Channel Attacks (SCA) like power analysis were successful in compromising this security.

This thesis focuses on designing effective countermeasures against the SCA's, by exploring the usage of an Asynchronous logic based design approach, called Null Convention Logic (NCL). This work discusses the design of NCL based subset of AES cryptosystem. The performance benefits of this novel cryptosystem are presented by making qualitative comparisons to the traditional synchronous design approach.

This thesis is composed of two papers. In paper I, the design and evaluation of SCA resistant NCL based AES Round Function is presented. This design approach leverages on the special properties of NCL to achieve a uniform and lower signal to noise ratio and thereby improves SCA resistance. Performance evaluation of the proposed design by using Weighed Average Simultaneous Switching Outputs (WASSO) analysis is presented. Paper II, discusses the design and evaluation of NCL based AES Key Expander, hardware implementation of the entire NCL based subset of AES cryptosystem on FPGA board. Performance evaluation of the proposed approach, by analyzing power traces obtained from hardware implementation of proposed design and the traditional synchronous design is presented. Using both the software simulations and hardware simulations the benefits of this proposed approach are discussed"--Abstract, page iv.


Choi, Minsu

Committee Member(s)

Zawodniok, Maciej Jan, 1975-
Shi, Yiyu


Electrical and Computer Engineering

Degree Name

M.S. in Computer Engineering


Missouri University of Science and Technology

Publication Date


Journal article titles appearing in thesis/dissertation

  • Design and evaluation of side channel attack resistant asynchronous AES Round Function.
  • Asynchronous AES key expander and round function design for improved SCA resistance


x, 65 pages

Note about bibliography

Includes bibliographical references.


© 2012 Siva Pavan Kumar Kotipalli, All rights reserved.

Document Type

Thesis - Open Access

File Type




Subject Headings

Data encryption (Computer science)
Data encryption (Computer science) -- Mathematical models
Logic circuits
Asynchronous transfer mode

Thesis Number

T 10053

Print OCLC #


Electronic OCLC #