"This thesis presents a method for performing an approximate synthesis of a variable delay time network by using RC elements and active analog computer circuits. The delay networks discussed here can provide delay times which range from zero to 96 milliseconds for inputs with frequencies which range between zero 2nd 5 cycles per second.
Basically, the procedure involves approximating the delay time transfer function, e-jwTd , by the ratio of two polynomials each of which is represented by a finite series of terms. The ratio is then shown to be easily synthesized by RC elements and analog computer circuits. The technique is illustrated by an appropriate example and the theoretical development is supported by experimental results.
Suggestions are also given which are useful in extending the time delay and input frequency range. These extensions are obtained by extending the number of series terms in the approximations of e-jwTd and by cascading several networks of the type described in this report"--Abstract p. 2
J. Robert Betten
Richard C. Harden
John August Nelson
Electrical and Computer Engineering
M.S. in Electrical Engineering
Missouri School of Mines and Metallurgy
vi, 51 pages
© 1963 Robert Sun-Wu Han, All rights reserved.
Thesis - Open Access
Print OCLC #
Han, Robert Sun-Wu, "A RC active delay time network." (1963). Masters Theses. 4448.