Keywords and Phrases
Chemically-Assembled Electronic Nanotechnology (CAEN)
"Nanotechnology has been shown to have the potential to replace the existing CMOS technology in the race to maintain the Moore's Law increases in IC complexity. This work considers the Chemically Assembled Electronic Nanotechnology (CAEN), which fabricates nanofabric using a low cost self-assembly and self-alignment chemical process and provides very high density. However, the main disadvantage of this technology is the inherently high defect rate that hinders the efforts to commercialize such systems. Existing testing and design techniques, for example for FPGAs, are ill suited since they typically assume vary low defect rates.
This thesis is comprised of two papers. In the paper I, a novel testing methodology is proposed along with a new set of test patterns and configurations which test the entire nanofabric for stuck-at, bridging and cross-point faults. An optimization technique is described to reduce the number of test configurations and testing time. A customization technique is also discussed to further increase the yield of the nanofabric when the desired functionality is known. Once the nanofabric has been tested and the faulty areas in the chip have been identified, the next step is to map the logic onto the nanofabric. The paper II discusses a new logic mapping approach for nanofabrics which have been tested to successfully implement AND/OR configurations of various logic functions. This approach uses the information provided by the testing technique from the paper I to simplify the logic mapping process. It used standard implementations of nanoblocks as compared to the existing techniques, which require customized solutions"--Abstract, page iv.
Zawodniok, Maciej Jan, 1975-
Beetner, Daryl G.
Electrical and Computer Engineering
M.S. in Computer Engineering
Missouri University of Science and Technology
Journal article titles appearing in thesis/dissertation
- Optimized testing technique for defect tolerance in CAEN-based nanofabric systems
- Introduction to a novel defect-aware logic mapping approach for crossbar-based nanofabrics
xi, 73 pages
© 2011 Sambhav Dilip Kundaikar, All rights reserved.
Thesis - Restricted Access
Fault tolerance (Engineering)
Print OCLC #
Electronic OCLC #
Link to Catalog Record
Electronic access to the full-text of this document is restricted to Missouri S&T users. Otherwise, request this publication directly from Missouri S&T Library or contact your local library.http://laurel.lso.missouri.edu/record=b8625329~S5
Kundaikar, Sambhav, "Optimized testing and logic mapping methodology for CAEN-based nano-circuits" (2011). Masters Theses. 4137.
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