Masters Theses
Abstract
"Nanotechnology is soon predicted to replace the CMOS technology, as current CMOS lithographic techniques will become void for complex IC designs with smaller feature size, and are hence incapable of keeping up with Moore's law. The devices in nanotechnology are fabricated using bottom up self-assembly. Memristor is one promising nanotech device which can replace the transistor used as a switch or memory device as it is just half the size and uses only fraction of the energy. This work considers Memristor Look Up Table (MLUT) design, which is a building block for asynchronous FPGAs built with memristors. In spite of having numerous merits over the clocked counterparts and previous asynchronous designs, it is bound to have inevitable defects due to non-deterministic nanoscale assembly. In order to assess the reliability of MLUT and ensure the efficient usage, there is a need to develop efficient testing and reconfiguration techniques.
This thesis is composed of two papers. In paper I, a novel testing scheme based on "Divide and Conquer" approach is proposed to efficiently locate the defective memristors in a MLUT. This scheme leverages on special current additive property of the memristor based multiplexer. Once the defects are located, there is a need to check if the defects can be tolerated and the defective MLUT still be used. Paper II discusses a hardware based reconfiguration scheme which relies on reusability of defective MLUTs by using the property of defect hiding. This approach uses the information provided by the testing algorithm in paper I. An efficient programming methodology based on the special property is introduced, which has a speed up of nearly 80% for device programming"--Abstract, page iv.
Advisor(s)
Choi, Minsu
Committee Member(s)
Zawodniok, Maciej Jan, 1975-
Shi, Yiyu
Department(s)
Electrical and Computer Engineering
Degree Name
M.S. in Computer Engineering
Publisher
Missouri University of Science and Technology
Publication Date
Fall 2011
Journal article titles appearing in thesis/dissertation
- Novel "Divide and Conquer" testing technique for Memristor based lookup table
Pagination
xi, 67 pages
Note about bibliography
Includes bibliographical references.
Rights
© 2011 Veeresh Anilkumar Hongal, All rights reserved.
Document Type
Thesis - Open Access
File Type
text
Language
English
Subject Headings
Computer programs -- Defects
Memristors -- Testing
Memristors
Synchronous data transmission systems
Thesis Number
T 9927
Print OCLC #
795403980
Electronic OCLC #
908456943
Recommended Citation
Hongal, Veeresh Anilkumar, "Memristor based lookup table - novel testing and reconfiguration techniques" (2011). Masters Theses. 4134.
https://scholarsmine.mst.edu/masters_theses/4134