Masters Theses

Keywords and Phrases

NULL Convention Logic circuits


"As the complexities of NULL Convention Logic circuits increase, the crucial role of design automation tools in virtually every aspect of NCL circuit design is undeniable. This thesis focuses on the design of several tools that can be used along with one of the industry standard digital design tools suites, Mentor Graphics, to automate and speedup the NCL design process. Hence, the tools are implemented as Tcl scripts, which can be run from within the Mentor Graphics toolset.

NCL design can be pipelined to increase throughput; thus, a pipelining tool is developed to automatically pipeline a given full-word dual-rail NCL design. Several algorithms are designed for pipelining the NCL design. The pipelining tool is applied to several NCL designs and the resulting pipelined designs are thoroughly tested for both correctness and speedup.

If the bit-wise completion strategy is used in lieu of full-word completion, throughput may be increased and area may be reduced. Hence, another tool to automatically convert a full-word pipelined design to a bit-wise pipelined design is developed and tested on several designs.

Third, an NCR tool is developed to automatically generate a Null Cycle Reduced version of a given dual-rail full-word completion NCL design, to increase the design's throughput. This is specifically useful to speed up a slow stage in an NCL pipeline that cannot be further pipelined. The NCR tool is applied to several NCL designs and the resulting NCR designs are thoroughly tested,

The key implementation details and methodology for the above tools are explained, and improvements are purposed for the next generation of asynchronous design automation tools. It is hoped that the development of design automation tools for asynchronous circuits will aid in the integration of this emerging paradigm into the semiconductor industry"--Abstract, page iii.


Scott C. Smith

Committee Member(s)

Hardy J. Pottinger
Daryl G. Beetner


Electrical and Computer Engineering

Degree Name

M.S. in Computer Engineering


University of Missouri--Rolla

Publication Date

Spring 2004


xi, 68 pages

Note about bibliography

includes bibliographical references (pages 66-67)


© 2004 Sasikanth Duggini, All rights reserved.

Document Type

Thesis - Restricted Access

File Type




Subject Headings

Logic circuits -- Design and construction

Thesis Number

T 8488

Print OCLC #


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