Keywords and Phrases
NULL Convention Logic (NCL)
"This thesis focuses on design and characterization of arithmetic circuits, such as multipliers and ALUs, using the asynchronous delay-insensitive NULL Convention Logic (NCL) paradigm. This work helps to build a library of reusable components to aid in the integration of asynchronous design paradigms, like NCL, into the semiconductor design industry.
A number of 4-bit x 4-bit unsigned multipliers are designed and characterized in terms of speed and area. The architectures under consideration are bit-serial, iterative, and fully parallel multiplication. The bit-serial and iterative multipliers are developed in the dual-rail domain, while the fully parallel architecture is designed in the quad-rail domain and compared to its equivalent dual-rail version, which was developed previously.
Furthermore, a number of 4-bit, 8-operation parallel arithmetic logic units (ALUs) are designed in the quad-rail domain, and are characterized in terms of speed and area. These versions include a non-pipelined design, an optimally pipelined design, a non- pipelined design utilizing NULL Cycle Reduction (NCR), a non-pipelined design with embedded registration, and a NULL Cycle Reduced non-pipelined design with embedded registration. Applying NCR to either non-pipelined quad-rail ALU significantly increases throughput compared to directly pipelining the ALU, while requiring approximately the same area. These quad-rail versions are then compared to their respective previously developed dual-rail counterparts"--Abstract, page iii.
Smith, Scott C.
Hubing, Todd H.
Beetner, Daryl G.
Electrical and Computer Engineering
M.S. in Computer Engineering
University of Missouri--Rolla
x, 67 pages
© 2003 Satish Kumar Bandapati, All rights reserved.
Thesis - Restricted Access
Computer arithmetic and logic units
Print OCLC #
Link to Catalog Record
Electronic access to the full-text of this document is restricted to Missouri S&T users. Otherwise, request this publication directly from Missouri S&T Library or contact your local library.http://merlin.lib.umsystem.edu/record=b5089517~S5
Bandapati, Satish K., "Design and characterization of asynchronous delay-insensitive arithmetic components using NULL conventional logic" (2003). Masters Theses. 2449.
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