Masters Theses
Design of a shift-register based ATM switch in VHDL
Department(s)
Electrical and Computer Engineering
Degree Name
M.S. in Electrical Engineering
Publisher
University of Missouri--Rolla
Publication Date
Fall 1999
Pagination
vii, 63 pages
Rights
© 1999 Sricharan Kasetti, All rights reserved.
Document Type
Thesis - Citation
File Type
text
Language
English
Thesis Number
T 7646
Print OCLC #
43067571
Link to Catalog Record
Full-text not available: Request this publication directly from Missouri S&T Library or contact your local library.
http://merlin.lib.umsystem.edu/record=b4256277~S5Recommended Citation
Kasetti, Sricharan, "Design of a shift-register based ATM switch in VHDL" (1999). Masters Theses. 1853.
https://scholarsmine.mst.edu/masters_theses/1853
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