A CN-FDTD Scheme and Its Application to VLSI Interconnects/Substrate Modeling
This document has been relocated to http://scholarsmine.mst.edu/ele_comeng_facwork/1338
There were 15 downloads as of 28 Jun 2016.
In this paper, a two-dimensional (2D) Crank-Nicholason (CN) finite difference time domain (FDTD) method is proposed for VLSI interconnect/substrate characterization. Through rigorous truncation and dispersion error analyses, a guideline on using this technique is presented. Several iterative solvers are investigated to accelerate the solution of the CN-FDTD scheme. Numerical examples are given to demonstrate the accuracy and the efficiency of the proposed algorithm.