Impact of ESD Generator Parameters on Failure Level in Fast CMOS System

Kai Wang
David Pommerenke, Missouri University of Science and Technology
Kai Xiao
Ponniah Ilavarasan
Mike Schaffer
Ramachandran Chundru
Jiu Sheng Huang

This document has been relocated to

There were 4 downloads as of 28 Jun 2016.


Electrostatic discharge (ESD) generators are used for testing the robustness of electronics towards ESD. Most generators are built in accordance with the IEC 61000-4-2 specifications. It is shown that the voltage induced in a small loop correlates with the failure level observed in an ESD failure test on the systems comprising fast CMOS devices, while rise time and current derivative of the discharge current did not correlate well. The electric parameters are compared for typical and modified ESD generators and the effect on the failure level of fast CMOS electronics is investigated. The consequences of aligning an ESD standard with the suggestions of this paper are discussed with respect to reproducibility and test severity.