To characterize additional conductor loss introduced by conductor surface roughness, various models have been proposed to describe the relationship between foil roughness levels and surface roughness correction factor. However, all these empirical or physical models require a PCB sample to be manufactured and analyzed in advance. The procedure requires dissecting the PCB and is time- and labor-consuming. To avoid such a process, a new surface roughness extraction process is proposed here. Only the measured S-parameter and nominal cross-sectional information of the board are needed to extract the roughness level of conductor foils. Besides, this method can also deal with boards having non-equal roughness on different conductor surfaces, which is common in the manufactured printed circuit boards (PCB). The roughness level on each surface can be extracted separately to accurately model their contribution to the total conductor loss. The presented method is validated by both simulation and measurement. A good correlation is achieved between extracted roughness level and the measured value from the microscope.


Engineering Management and Systems Engineering

Second Department

Electrical and Computer Engineering


National Science Foundation, Grant IIP-1916535

Keywords and Phrases

printed circuit board; signal integrity; striplines; Surface roughness

International Standard Book Number (ISBN)


Document Type

Article - Conference proceedings

Document Version

Final Version

File Type





© 2023 Institute of Electrical and Electronics Engineers, All rights reserved.

Publication Date

01 Jan 2022